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#1 May 12, 2018
alibaba996
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Basic MOS Problem

Hi everybody,

My question is maybe a very fundemental problem but ı can't deal with it. So as it seems  although ı grounded gate  of mos's ,Circuit still voltage divide. Therefore it cause logic errors in cascade situation. How can ı solve this problem?

Thank you already

 

https://ibb.co/b18EOy

Mon, 2018-05-14 07:56
Idris
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When turned off a MOS has a very high resistance, but still finite. In your circuit, you used three devices of the same type so you'll have three identical resistors in series. Can you tell us what you hope to achieve?

Mon, 2018-05-14 08:42
alibaba996
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Actually when ı turned off a mos it behave like insulator in practice . So we cant use voltage division on insulator. 

Mon, 2018-05-14 08:58
Idris
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In PSpice these devices are modeled as very high resistances when off. So Imagine having a three 4 gigaohm resistors in series. To the simulator that's a voltage divider. Also, suppose there's an inuslator between the first transistor's drain and ground, what would the voltage be? PSpice can't calculate "floating" voltages, and neither can you.

Mon, 2018-05-14 09:15
alibaba996
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I get the point. Thanks but ı want to realize a cascade digital gates. Therefore ı drive capacitive loads. Because of this voltage dividing ı get false outputs. İs there any way that ı can make this solve this

Mon, 2018-05-14 10:17
Idris
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In CMOS digital circuits, you most likely find a Pull down network (made with NMOS like the circuit you provided) and a Pullup network (made of PMOS).

In this case, I'm assuming you're building a three input AND gate? You will have to add a Pullup network made of three PMOSs in parallel between the positive rail and the output. You will have to add an inverter at the output.

I would also advice to use MbreakN and MbreakP from Breakout.OLB because you can customize these devices (W, L, Kn'...)

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