Mitigating Design Risks Quickly via Scalable Circuit Simulation with PSpice and OrCAD Solutions
Whether you’re listening to your favorite album, rocking out at a live concert, or watching the evening news, your experience wouldn’t be as enjoyable without excellent sound quality. One of the leaders behind this sound quality is Oxfordshire, UK-based Solid State Logic. Founded in 1969, the professional audio manufacturer develops analog and digital mixing and sound consoles for studio, live, and broadcast environments.
Some products are entirely analog designs, while others are mixed signal. Complex design sub-circuits, such as preamplifiers, consist of up to 100 discrete components that contribute to product differentiation.
While many of Solid State Logic’s products have fairly long shelf lives, the company’s team of hardware engineers—who design hardware, write firmware, and design PCBs—are expected to support periodic product updates. “We need to keep our products relevant and competitive,” said Glen Pratley, hardware design team leader. “We’re constantly pushing ourselves to deliver new replacements or keep our existing products relevant by adding new features.”
Typically, the company launches new products at trade shows, so they can’t miss these market opportunities. Noted Charles Pickers, senior hardware engineer, “We can’t afford the extra time of lots of board respins. And, it’s important that our tools remain relevant and useful, since we can’t afford to keep changing the tools.”
With such aggressive timelines as well as an ever-present pressure to deliver the highest quality sound equipment, Solid State Logic needed to be able to accurately simulate and optimize its circuits well before committing them to manufacturing. The company has been a long-time user of legacy circuit simulation tools. They switched to Cadence’s simulation tools because these tools offered advanced capabilities with scalability and a price point that represented excellent value for Solid State Logic’s money.
After evaluating the available options, Solid State Logic decided to migrate its schematic-to-simulation-to-board layout flow to one based on the Cadence® OrCAD product family with PSpice, which met all its requirements. The centerpiece of their flow is OrCAD PSpice Designer, which provides advanced circuit simulation and analysis for analog and mixed-signal circuits. The team uses OrCAD Capture CIS for schematic design and OrCAD Professional and Allegro PCB Designer for PCB layout design. The team also uses the SigXplorer module of Allegro Sigrity SI, which provides a topology exploration tool for signal and power integrity assessment.
“OrCAD PSpice Designer does everything that we need and it is scalable, providing everything from low-end seats for tasks like placement and viewing to higher level tools for the heavier lifting of circuit design,” explained Pratley. “With PSpice technology, we can mitigate many design risks before committing to copper.
Initially, it was challenging for designers long accustomed to their legacy environment—and under the pressure of tight deadlines— to make a switch. But with strong support from Parallel Systems (the UK Cadence Channel Partner), the experienced engineering team ramped up quickly into their new environment. Today, all new designs from Solid State Logic—including the recently announced System T next-generation, large-scale broadcast console (Figure 1) —are built with a Cadence circuit simulation and PCB design flow.
Figure 1: Solid State Logic's Systems T flagship broadcast console for large-scale productions
With their Cadence PCB design flow, Solid State Logic can achieve first-time-right design accuracy, which helps the team meet their aggressive product delivery deadlines while giving them the ability to quickly release product upgrades. Previously manual tasks, such as managing ground planes, are easier to do with the automation available in Allegro PCB Designer. With OrCAD Capture CIS, the team is more closely aligned when it comes to managing their electrical components, which helps accelerate their design process and control their costs.
Since migrating to the Cadence flow, the design team has built up a large set of components and reference designs. From their catalog of work, they can cut and paste existing components into new designs, which speeds up the design process for new and upgraded products. There is also available a large body of PSpice models, so the team hasn’t had to write any of its own simulation models. “With the majority of IC vendors providing PSpice simulation models, we’ve never had to create our own simulation models. This has helped improve our productivity, saving us weeks to several months since we don’t have to create any complex simulation models ourselves.” said Pratley.
Pratley and Pickers can share a few tips learned through their experiences. In OrCAD PSpice Designer, they’ve found the hierarchical simulation capability useful in modeling microphone preamplifer circuits, which can have up to 100 discrete components for a single channel. Using the capability, they can evaluate circuit characteristics, create a copy in another hierarchical block, do some modeling, compare this with the original, and then use the model as a benchmark.
Many of the company’s products operate in extreme environments (for example, an outdoor concert on a hot, humid day). With a collection of benchmark simulations, the design team can easily evaluate the behavior of, say, an amplifier and make adjustments for a range of extreme temperatures.
Looking ahead, Solid State Logic plans to evaluate additional simulation and design capabilities to add to their flow. For example, the design team often uses FPGAs and plans to have a look at OrCAD FPGA System Planner for support in creating placement- aware initial pin assignments for an FPGA.
“We’re very optimistic about our future and, with our scalable Cadence circuit simulation and design tool flow with OrCAD Capture CIS with PSpice and Allegro PCB Designer tools, we have an environment that will grow with us as our needs change,” said Pratley.