*hello
* PSpice Model Editor - Version 16.3.0
*$
*-------------------------------------------------------------------------
*
*  74116 DUAL 4-BIT LATCHES WITH CLEAR
*
*  The TTL Data Book, Vol 2, 1985, TI
*  MCG 07/09/93
*
.SUBCKT 74116 C1BAR_I C2BAR_I CLRBAR_I D1_I D2_I D3_I D4_I  Q1 Q2 Q3 Q4
+ optional: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
*
U116_1 BUFA(7) DPWR  DGND
+ D1_I D2_I D3_I D4_I C1BAR_I C2BAR_I CLRBAR_I
+ D1   D2   D3   D4   C1BAR   C2BAR   CLRBAR
+ D0_GATE IO_STD
*
U116_2 DLTCH(4)
+ DPWR  DGND
+ $D_HI CLRBAR LAT
+ D1    D2    D3    D4
+ Q1    Q2    Q3    Q4
+ $D_NC $D_NC $D_NC $D_NC
+ D_74116 IO_STD 
*
U116_3 INVA(2)
+ DPWR  DGND
+ C1BAR C2BAR 
+ C1    C2    
+ D0_GATE IO_STD 
*
U116_4 AND(2)
+ DPWR  DGND
+ C1    C2
+ LAT
+ D0_GATE IO_STD 
*
U116CON CONSTRAINT(7) DPWR DGND
+ CLRBAR C1BAR C2BAR D1 D2 D3 D4 
+ IO_STD
+
+ WIDTH:
+   NODE = CLRBAR
+   MIN_LO = 18NS
+   MIN_HI = 18NS
+
+ WIDTH:
+   NODE = C1BAR
+   MIN_LO = 18NS
+   MIN_HI = 18NS
+
+ WIDTH:
+   NODE = C2BAR
+   MIN_LO = 18NS
+   MIN_HI = 18NS
+
+ SETUP_HOLD:
+   DATA(4) D1 D2 D3 D4
+   CLOCK LH = C1BAR
+   SETUPTIME_HI =  8NS
+   SETUPTIME_LO = 14NS
+   RELEASETIME  =  2NS
+   HOLDTIME     =  8NS
+
+ SETUP_HOLD:
+   DATA(4) D1 D2 D3 D4
+   CLOCK LH = C2BAR
+   SETUPTIME_HI =  8NS
+   SETUPTIME_LO = 14NS
+   RELEASETIME  =  2NS
+   HOLDTIME     =  8NS
+
+ SETUP_HOLD:
+   DATA(1) C1BAR 
+   CLOCK LH = CLRBAR
+   SETUPTIME    =  8NS
*
.ENDS
*$
.SUBCKT peakmeter input output PARAMS: DELAY={100u}
T_T2         B 0 C 0 Z0=1k TD={Delay}  
T_T1         N16919 0 B 0 Z0=1k TD={Delay}  
R_R1         C 0 1k TC=0,0 
E_GAIN2         OUTPUT 0 VALUE {1 * V(N16975)}
E_ABM1         N16975 0 VALUE { If((V(B)>v(INPUT) & (V(B)>v(C))),v(B),If((V(B)<v(INPUT) & (V(B)<v(C))),v(B),0))}
E_GAIN1         N16919 0 VALUE {1 * V(INPUT)}
R_R2         0 N16919 1k TC=0,0 
.ENDS
*$
.SUBCKT analogdelay in out PARAMS: DELAY ={1u}
R_R1         0 N00098  1k  
R_R2         0 N00105  1k  
T_T1         N00098 0 N00105 0 Z0=1k TD={Delay}  
E_GAIN1         N00098 0 VALUE {1 * V(IN)}
E_GAIN2         OUT 0 VALUE {1 * V(N00105)}
.ENDS
*$
.SUBCKT 	DIAC32 1 2 
RS 1 6 10 
RV 2 4 510k 
R1 6 2 10k 
R2 4 2 10k 
Q4 2 5 2 0 PNP 
Q2 4 3 6 0 PNP 
Q1 3 4 2 0 NPN 
Q3 5 2 6 0 NPN 
D5 2 5 D 
D6 4 3 D 
.model NPN NPN(BF=20 TF=5u) 
.model PNP PNP(BF=2 TF=5u) 
.model D D 
.ENDS *Default N-Channel Unijunction Transistor
*$
*****************************************************************
.SUBCKT 2N6027 1 2 3
**************************************
*      Model Generated by CZ LAB     *
*           April 20, 2001           *
*   Copyright(c) On Semiconductor    *
*         All Rights Reserved        *
*Commercial Use or Resale Restricted *
**************************************
*Programable Unijunction Transistor
*MODEL FORMAT: PSpice
*       anode  gate  cathode
*node:    1      2      3
Q1 2 4 3 NMOD Q2 4 2 1 PMOD 
.MODEL NMOD NPN(IS=5E-15 VAF=100 IKF=0.3 ISE=1.85E-12
+ NE=1.45 RE=0.15 RC=0.15 CJE=7E-10 TF=0.6E-8
+ CJC=2.2E-10 TR=4.76E-8 XTB=3) 
.MODEL PMOD PNP(IS=2E-15 VAF=100 IKF=0.3 ISE=1.90E-12
+ NE=1.5 RE=0.15 RC=0.15 CJE=7E-10 TF=1.6E-8
+ CJC=2.2E-10 TR=5.1E-8 XTB=3) 
.ENDS
*$
.SUBCKT 2N2646 1 2 3
DE 1 4 emitter
VE 4 5 DC 0
HVE 6 0 VE 1K
RVE 0 6 1MEG
BBB 5 7 I=0.00028*V(5,7)+0.00575*V(5,7)*V(6)
CBB 5 7 35P
RB1 7 2 38.15 RMOD
RB2 3 5 2.518K RMOD 
.MODEL RMOD R TC1=.01
.MODEL emitter D (IS=21.3P N=1.8)
.ENDS 2N2646
*$
**************************************************************
*  AD8041a Spice Macro-model                  9/96, Rev A
*
*  Copyright 1996 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement.
* Use of this model indicates your acceptance with
* the terms and provisions in the License Statement.
*
* The following parameters are accurately modeled;
*
*    open loop gain and phase vs frequency
*    output clamping voltage and current
*    input common mode range
*    CMRR vs freq
*    I bias vs Vcm in    
*    Slew rate
*    Output currents are reflected to V supplies
*
*    Vos is static and will not vary with Vcm in
*    Step response is modeled at unity gain w/1k load 
*
*    Distortion and noise are not characterized
*
*    Node assignments
*                non-inverting input
*                | inverting input
*                | | positive supply
*                | | |  negative supply
*                | | |  |  output
*                | | |  |  |
.SUBCKT AD8041a  1 2 99 50 61 
***** Input bias current source
ecm 20 0 99 3 1 
d1 20 21 dx
v3 21 22 0.2
r20 22 0 100
f1 0 25 v3 1 
r22 25 0 1k
r23 26 28 8
d3 25 26 dx
v5 28 0 .3
g1 1 0 0 25 400e-9
g2 2 0 0 25 400e-9
***** Input Stage
R1 1 3 80k
R2 3 2 80k
C1 1 2 1.8pf
rcm1 1 0 5e6
rcm2 2 0 5e6
R3 1 98 40e6
R4 2 98 40e6 
r9 15 7 764
r10 16 7 764
q1 5 1 15 qp1
q2 6 4 16 qp1
r5 50 5 1254
r6 50 6 1254
ib3 99 7 1e-4
eos 2 4 poly(1) (108,98) 2e-3 1
***** gain stage/pole at 3200hz/clamp circuitry
g3 99 31 6 5 7.97e-4
g4 31 50 5 6 7.97e-4
r7 99 31 63e6
r8 31 50 63e6
c3 99 31 0.635e-12
c4 31 50 0.635e-12
vc1 99 45 0.72
vc2 46 50 0.72
dc1 31 45 dx
dc2 46 31 dx
***** pole at 200mhz
e1 32 98 31 98 1
rflt 32 33 1k
cflt 33 98 0.796e-12
***** internal reference
rdiv1 99 97 100k
rdiv2 97 50 100k
Eref 98 0 97 0 1
rref 98 0 1e6
***** Common mode gain network
gacm1 99 100 3 98 2e-13
gacm2 100 50 98 3 2e-13
racm1 99 100 1e4
racm2 100 50 1e4
***** Common mode gain network/zero at 3200hz 
ecm1  101 98 100 98 1e6 
racm3 101 102 1e6
racm4 102 103 1
lacm1 103 98 40u
***** Common mode gain network/zero at 100khz/pole at 60mhz
ecm2  104 98 102 98 300
racm5 104 105 300
racm6 105 106 1
lacm2 106 98 .78u
***** Common mode gain network/pole at 60mhz
ecm3 107 98 105 98 1 
racm7 107 108 10k
cacm1 108 98 0.265e-12
***** buffer to output stage
gbuf 98 34 33 98 1e-4
re1 34 98 10k
***** output stage
fo1 98 110 vcd 1
do1 110 111 dx
do2 112 110 dx
vi1 111 98 0
vi2 98 112 0
fsy 99 50 poly(2) vi1 vi2 4.73e-3 1 1
go3 60 99 99 34 0.1
go4 50 60 34 50 0.1
r03 60 99 10
r04 60 50 10
vcd 60 62 0
lo1 62 61 2n
ro2 61 98 1e9
do5 34 70 dx
do6 71 34 dx
vo1 70 60 -0.31
vo2 60 71 -0.05
.model dx d(is=1e-15)
.model qn1 npn(bf=500 vaf=100)
.model qp1 pnp(bf=500 vaf=60)
.ends ad8041a
*$
**************************************************************
.subckt CD4046-X sigin phcmpii phcmpi phpls compin vcoin
+              r1 r2 ce1 ce2 vcoout demout inhibit zener vdd vss
+                   OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+                   PARAMS: MNTYMXDLY=0 IO_LEVEL=0
+                   Rin=1Meg S1=1  S2=0.5 M1=0.5 M2=1.0 Vx=10
+                   Kb=1 Vfree=0.0 Kc=-0.1 Vt=1.2 Vxqr=10
* Rin  = VCO Input Resistace
* S1   = Voltage Limiter linear slope
* S2   = Voltage Limiter non-linear slope
* Vx   = Input threshold voltage (between S1 and S2)
* Kb   = Arbitrary constant to adjust the value of the conversion gain (transimpedance gain)
* Vfree= Frequency dependent constant in Emult
* Kc   = Negative inverse amplitude of the square wave
* Vt   = Trigger voltage of Schmitt trigger (not used)
* Vxqr = Amplitude of square wave (not used)
* M1   = Current mirror multiplier to adjust oscillator frequency
* M2   = Current mirror multiplier to adjust oscillator frequency
* Preliminary model still under development based on Natinal Semiconductor CD4046BM
* RAPerez 9/98
* Phase detector section
U1 INVA(4) DPWR DGND sigin compin isigin icompin  
+                    isigin icompin clk1 clk2 
+ INVA_TIMING IO_STD
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL INVA_TIMING UGATE
U2 XOR DPWR DGND isigin icompin xorout
+ XOR_TIMING IO_STD
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL XOR_TIMING UGATE 
***tplhty=20n tphlty=20n
U3 NAND(2) DPWR DGND q1 q2 pclr
+ NAND_TIMING IO_STD
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL NAND_TIMING UGATE (tplhty=1n tphlty=1n)
U4 DFF(1) DPWR DGND $D_HI clr clk1 $D_HI q1 qb1
+ DFF1_TIMING IO_STD
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DFF1_TIMING UEFF tppcqlhty=4n tppcqhlty=4n tpclkqlhty=4n tpclkqhlty=4n
U5 DFF(1) DPWR DGND $D_HI clr clk2 $D_HI q2 qb2
+ DFF2_TIMING IO_STD
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DFF2_TIMING UEFF tppcqlhty=5n tppcqhlty=5n tpclkqlhty=5n tpclkqhlty=5n
U7 BUFA(2) DPWR DGND fq1 fq2 s1 s2
+ BUFA_TIMING IO_STD
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL BUFA_TIMING UGATE
ST2 vdd phcmpii s1 0 swt
SB2 phcmpii vss s2 0 swt
.model swt VSWITCH (ROFF=2G RON=10m VOFF=0.8 VON=3.0)
U6 AND(2) DPWR DGND pclr reset clr
+ AND_TIMING IO_STD
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL AND_TIMING UGATE
Ureset STIM(1,1) DPWR DGND 
+ reset
+ IO_STD
+   +0s 0
+   2ns 1
+   1s 1
U8 NOR(2) DPWR DGND fq1 fq2 norout
+ NOR_TIMING IO_STD
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL NOR_TIMING UGATE
U9 ANDA(2,2) DPWR DGND q1 od1 q2 od2 fq1 fq2
+ ANDA_TIMING IO_STD
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL ANDA_TIMING UGATE
U10 DLYLINE DPWR DGND q1 od1
+ DLY_TIMING IO_STD
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U11 DLYLINE DPWR DGND q2 od2
+ DLY_TIMING IO_STD
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_TIMING UDLY dlyty=12n
U12 BUFA(3) DPWR DGND norout xorout vcosqr phpls phcmpi vcoout
+ BUFB_TIMING IO_STD
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL BUFB_TIMING UGATE
* VCO Section
Rin vcoin vss {Rin}
Evlim vlim 0 value={if(v(vcoin,vss)<v(vdd,vss),
+                   S1*v(vcoin,vss),S2*(v(vcoin,vss)-v(vdd,vss))+v(vdd,vss))}
Rvlim vlim 0 1Meg
Emult mix 0 value={v(vlim)*Kb+Vfree}
*Hmult mix 0 poly(1) Vcm 1.44 0.586
Rmult mix 0 1
Edemout demout 0 table={ 200Meg*v(vcoin,demout)*v(off) } (-20,-20) (20,20)
Rdemout demout 0 1Meg
ER2 ir2 0 vdd ir2 200Meg
VR2 ir2 r2
ER1 ir1 0 mix ir1 200Meg
VR1 ir1 r1
Eosclg adj 0 table={abs((V(vdd)/I(VR2))/(V(mix)/I(VR1)))}
+ (0.5,1.43) (1,1.6) (10,1.04) (50,0.67) (100,0.84) (101,1)
+ (102,1) (1000,1)
Radj adj 0 1G
*GIM ce1 0 value={(M1*I(VR1)+M2*I(VR2))*Kc*V(sqrrc)}
GIM ce1 0 value={(M1*I(VR1)*V(adj)+M2*I(VR2))*Kc*V(sqrrc)}
*GIM ce1 0 value={(24*I(VR1)+3.067*I(VR2))}
Vcext ce2 0
Cstray ce1 ce2 6p
Rcext ce1 ce2 1T
Etrngl trngl 0 ce1 0 1
Rtrngl trngl 0 1Meg
Esqr sqr 0 value={-10Meg*V(trngl)+1.2Meg*V(sqrrc)} 
Rsqr sqr sqrrc 0.1T
Csqr sqrrc 0 10f
Dsqr1 sqrrc 13 Diode
Vsqr1 13 0 {Vx}
Dsqr2 14 sqrrc Diode
.model Diode D (IS=10u N=0.1 CJO=80f RS=1m)
*.model Diode D (IS=10u N=0.001 CJO=80f)
Vsqr2 14 0 {-Vx}
Ipls 0 sqrrc pwl 0 0 10n 0 20n 0.01u 0.1u 0.01u 0.12u 0 1 0
Evcoout vcosqr 0 table={5.0*v(off)*(v(sqrrc)/Vx)} (0.1,0.1) (4.5,4.5) 
*Rvcoout vcosqr vcosqr1 1
**Et 7 0 TABLE {-10k*V(trngl)+1.2k*V(sqrrc)} (-2,-10) (2,10)
*Ipls 0 sqrrc pwl 0 0 10n 0 20n 1u 0.1u 1u 0.12u 0 1 0
*Et 7 0 value={table({-10Meg*V(trngl)+1.2Meg*V(sqrrc)},-10,{-Vx},10,{Vx})}
*Ro 7 sqrrc 100
*Co sqrrc 0 100p 
*Est sqrrc o VALUE={table({2000k*(V(st)-V(trngl))},-2,{-Vx},2,{Vx})}
*Rst1 sqrrc st 8.8k
*Rst2 st 0 1.2k
*Cst st 0 200p ic=-10
Rinhbt inhibit 0 1Meg
Eoff off 0 value={if(v(inhibit)<0.9,1.0,0.0)}
Roff off 0 1Meg
Dzener vss zener znr
Rzener vss zener 1G
.model znr	D(Is=1.004f Rs=.5875 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=160p M=.5484
+		Vj=.75 Fc=.5 Isr=1.8n Nr=2 Bv=5.2 Ibv=27.721m Nbv=1.1779
+		Ibvl=1.1646m Nbvl=21.894 Tbv1=176.47u)
.ends
*$
****************
.model TIP31   NPN(Is=2.447p Xti=3 Eg=1.11 Vaf=100 Bf=208.2 Ise=70.69p
+               Ne=1.565 Ikf=.9743 Nk=.6134 Xtb=1.5 Br=12.59 Isc=11.68n
+               Nc=1.835 Ikr=3.86 Rc=.4685 Cjc=142p Mjc=.4353 Vjc=.75 Fc=.5
+               Cje=188.5p Mje=.4878 Vje=.75 Tr=194.2n Tf=19.85n Itf=164.1
+               Xtf=5.945 Vtf=10 Rb=.1)
*		National Semiconductor
*		Transistor Databook, 1982, process 4F, pg 9-13
*		30 Nov 90	pwt	creation
*$
.model TIP32   PNP(Is=51.23f Xti=3 Eg=1.11 Vaf=100 Bf=434.1 Ise=51.23f Ne=1.22
+               Ikf=.3883 Nk=.5544 Xtb=2.2 Br=55.47 Isc=51.23f Nc=1.205
+               Ikr=10.87 Rc=.3443 Cjc=136.9p Mjc=.3155 Vjc=.75 Fc=.5
+               Cje=179.9p Mje=.4294 Vje=.75 Tr=20.25n Tf=13.05n Itf=6.85
+               Xtf=1.573 Vtf=10 Rb=.1)
*		National Semiconductor
*		Transistor Databook, 1982, process 5F, pg 9-36
*		30 Nov 90	pwt	creation
.ends
*$
**********************************************************************
* GENERIC: 12AX7 / ECC83
* MODEL:   NH12AX7
* NOTES:   No heater model
**********************************************************************
.SUBCKT 12AX7A A G K
XV1 A G K TRIODENH
+PARAMS: LIP= 1.5 LIF= 0.000016 RAF= 0.076498 RAS= 1 CDO=-0.53056 
+ RAP= 0.18 ERP= 1.5 
+ MU0= 87.302 MUR=-0.013621 EMC= 0.00000111 
+ GCO=-0.2 GCF= 0.00001 
+ CGA=3.90E-12 CGK=2.40E-12 CAK=7.00E-13
.ENDS
*$
.SUBCKT TRIODENH A G K
+PARAMS: LIP=1 LIF=3.7E-3 RAF=18E-3 RAS=1 CDO=0 RAP=4E-3
+ ERP=1.5
+ MU0=17.3 MUR=19E-3 EMC=9.6E-6 GCO=0 GCF=213E-6
+ CGA=3.9p CGK=2.4p CAK=0.7p 
************************************************************************
*
* Anode/grid model
*
* Models reduction in mu at large negative grid voltages
* Models change in Ra with negative grid voltages
* Models limit in Ia with high +Vg and low Va
*
* PARAMETERS
*
*	LIP Conduction limit exponent
*	LIF Conduction limit factor
*	CDO Conduction offset
*	RAF Anode resistance factor for neg grid voltages
*	RAP Anode resistance factor for positive grid voltages
*	ERP Emission power
*	MU0 Mu between grid and anode at Vg=0
*	MUR Mu reduction factor for large negative grid voltages
*	EMC Emission coefficient
*	GCO Grid current offset in volts
*	GCF Grid current scale factor
*
************************************************************************
Elim  LI 0  VALUE {PWR(LIMIT(V(A,K),0,1E6),{LIP})*{LIF}}
Egg   GG 0  VALUE {V(G,K)-{CDO}}
Erpf  RP 0  VALUE {1-PWR(LIMIT(-V(GG)*{RAF},0,0.999),{RAS})+LIMIT(V(GG),0,1E6)*{RAP}}
Egr   GR 0  VALUE {LIMIT(V(GG),0,1E6)+LIMIT((V(GG))*(1+V(GG)*{MUR}),0,-1E6)}
Eem   EM 0  VALUE {LIMIT(V(A,K)+V(GR)*{MU0},0,1E6)}
Eep   EP 0  VALUE {PWR(V(EM),ERP)*{EMC}*V(RP)}
Eel   EL 0  VALUE {LIMIT(V(EP),0,V(LI))}
Eld   LD 0  VALUE {LIMIT(V(EP)-V(LI),0,1E6)}
Ga    A  K  VALUE {V(EL)}
************************************************************************
*
* Grid current model
*
* Models grid current, along with rise in grid current at low Va
*
************************************************************************
Egf   GF 0  VALUE {PWR(LIMIT(V(G,K)-{GCO},0,1E6),1.5)*{GCF}}
Gg    G  K  VALUE {(V(GF)+V(LD))}
*
* Capacitances and anti-float resistors
*
CM1	G	K	{CGK}
CM2	A	G	{CGA}
CM3	A	K	{CAK}
RF1	A	0	1000MEG
RF2	G	0	1000MEG
RF3	K	0	1000MEG
.ENDS
*$
* 6DJ8/ECC88/6922/E88CC Triode PSpice Model
* copyright (c) 1998 Mithat Konar -- all rights reserved
* Model used: "Improved VT Models for SPICE Simulations,"
*     Norman Koren, Glass Audio 5/96.
* Plate parameters determined by computerized optimization, Jan 29, 1998.
* Plate data from http://www.mclink.it/com/audiomatica/sofia/.
* Interelectrode capacitances are based on data given for Amperex 6922/E88CC;
* however, the reliability of the HF characteristics for this model is probably
* not very high. It is likely that that additional complexity will be required
* to better model the HF behavior--including the inclusion of heater terminals
* in order to explicitly incorporate grid, plate, and cathode to heater
* capacitances. And don't forget to add parasitic capacitances of ~0.7 pF
* for adjacent pins and ~0.5 pF for others (see Koren's article) as well as for
* the effects of a shield (if used).
* No guarantees of any kind are made regarding the accuracy or suitability
* of any part of this model. Use at your own risk.
*
* Connections: Plate
*              | Grid
*              | | Cathode
*              | | |
.SUBCKT 6DJ8   1 2 3
+ PARAMS: MU=35.7 EX=1.35 KG1=274 KP=305 KVB=310
+ RGI=2000
+ CCG=3.1P CGP=1.4P CCP=0.45P ;
E1	7 	0	VALUE=
+{V(1,3)/KP*LOG(1+EXP(KP*(1/MU+V(2,3)/SQRT(KVB+V(1,3)*V(1,3)))))}
RE1	7	0	1G
G1	1	3	VALUE={ (PWR(V(7),EX)+PWRS(V(7), EX))/KG1 }
RCP	1	3	1G		; TO AVOID FLOATING NODES IN MU-FOLLOWER
C1	2	3	{CCG}	; CATHODE GRID
C2	2	1	{CGP}	; GRID-PLATE
C3	1	3	{CCP}	; CATHODE-PLATE
D3	5	3	DX		; FOR GRID CURRENT
R1	2	5	{RGI}	; FOR GRID CURRENT
.MODEL DX D(IS=1N RS=1 CJO=10PF TT=1N)
.ENDS 6DJ8
*$
.SUBCKT mc12148 GND IN OUT
E_TABLE1         IN 0 TABLE {V(IN)} 0.5V    -3.48V  
+ 1.0V    -3.24V  
+ 1.5V    -2.78V  
+ 2.0V    -2.37V  
+ 2.5V    -2.01V  
+ 3.0V    -1.69V  
+ 3.5V    -1.38V  
+ 4.0V    -1.02V  
+ 4.5V    -0.62V  
+ 4.75V   -0.40V  
+ 5.0V    -0.18V  
+ 5.5V    0.36V  
+ 6.0V    0.93V  
+ 6.5V    1.60V  
+ 7.0V    2.31V  
+ 7.5V    3.11V  
+ 8.0V    3.96V  
+ 8.5V    4.98V  
+ 9.0V    5.82V  
+ 9.5V    6.22V  
+ 10.0V   6.36V
E_E1         OUT 0 VALUE {sin(2*pi*(2.25*(V(IN,GND))+13.7)*1Meg*time)}
.PARAM  pi= 3.14159265359
.ENDS   MC12148
*$
* ad633 analog multiplier macro model 12/93, rev. a
* aag/pmi
*
* copyright 1993 by analog devices, inc.
*
* refer to "readme.doc" file for license statement.  use of this model
* indicates your acceptance with the terms and provisions in the license statement.
*
* node assignments
*             x1
*             |  x2
*             |  |  y1
*             |  |  |  y2
*             |  |  |  |  vneg
*             |  |  |  |  |  z
*             |  |  |  |  |  |  w
*             |  |  |  |  |  |  |  vpos
*             |  |  |  |  |  |  |  |
.subckt ad633 1  2  3  4  5  6  7  8
*
EREF 100 0 POLY(2) 8 0 5 0 (0,0.5,0.5)
*
* X-INPUT STAGE & POLE AT 15 MHz
*
IBX1 1 0 DC 8E-7
IBX2 2 0 DC 8E-7
EOSX 10 1 POLY(1) (16,100) (5E-3,1)
RX1A 10 11 5E6
RX1B 11 2 5E6
*
GX 100 12 10 2 1E-6
RX 12 100 1E6
CX 12 100 1.061E-14
VX1 8 13 DC 3.05
DX1 12 13 DX
VX2 14 5 DC 3.05
DX2 14 12 DX
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 560 Hz
*
ECMX 15 100 11 100 10
RCMX1 15 16 1E6
CCMX 15 16 2.8421E-10
RCMX2 16 100 1
*
* Y-INPUT STAGE & POLE AT 15 MHz
*
IBY1 3 0 DC 8E-7
IBY2 4 0 DC 8E-7
EOSY 20 3 POLY(1) (26,100) (5E-3,1)
RY1A 20 21 5E6
RY1B 21 4 5E6
*
GY 100 22 20 4 1E-6
RY 22 100 1E6
CY 22 100 1.061E-14
VY1 8 23 DC 3.05
DY1 22 23 DX
VY2 24 5 DC 3.05
DY2 24 22 DX
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 560 Hz
*
ECMY 25 100 21 100 10
RCMY1 25 26 1E6
CCMY 25 26 2.8421E-10
RCMY2 26 100 1
*
* Z-INPUT STAGE & POLE AT 15 MHz
*
IBZ1 7 0 DC 8E-7
IBZ2 6 0 DC 8E-7
RZ1 7 6 10E6
*
GZ 100 32 7 6 1E-6
RZ2 32 100 1E6
CZ 32 100 1.061E-14
VZ1 8 33 DC 3.05
DZ1 32 33 DX
VZ2 34 5 DC 3.05
DZ2 34 33 DX
*
* 50-MHz MULTIPLIER CORE & SUMMER
*
GXY 100 40 POLY(2) (12,100) (22,100) (0,0,0,0,0.1E-6)
RXY 40 100 1E6
CXY 40 100 3.1831E-15
*
* OP AMP INPUT STAGE
*
VOOS 59 40 DC 5E-3
Q1 55 32 60 QX
Q2 56 59 61 QX
R1 8 55 3.1831E4
R2 60 54 3.1313E4
R3 8 56 3.1831E4
R4 61 54 3.1313E4
I1 54 5 1E-4
*
* GAIN STAGE & DOMINANT POLE AT 316.23 Hz
*
G1 100 62 55 56 3.141637E-5
R5 62 100 1.0066E8
C3 62 100 5E-12
V1 8 63 DC 4.3399
D1 62 63 DX
V2 64 5 DC 4.3399
D2 64 62 DX
*
* NEGATIVE ZERO AT 20 MHz
*
ENZ 65 100 62 100 1E6
RNZ1 65 66 1
FNZ 65 66 VNC -1
RNZ2 66 100 1E-6
ENC 67 0 65 66 1
CNZ 67 68 7.9577E-9
VNC 68 0 DC 0
*
* POLE AT 4 MHz
*
G2 100 69 66 100 1E-6
R6 69 100 1E6
C2 69 100 3.9789E-14
*
* OP AMP OUTPUT STAGE
*
FSY 8 5 POLY(2) VZC1 VZC2 (2.8286E-3,1,1)
RDC 8 5 28E3
GZC 100 73 72 69 11.623E-3
VZC1 74 100 DC 0
DZC1 73 74 DX
VZC2 100 75 DC 0
DZC2 75 73 DX
VSC1 70 72 0.695
DSC1 69 70 DX
VSC2 72 71 0.695
DSC2 71 69 DX
GO1 72 8 8 69 11.623E-3 
RO1 8 72 86
GO2 5 72 69 5 11.623E-3 
RO2 72 5 86
LO 72 7 1E-7
*
* MODELS USED
*
.MODEL QX NPN(BF=1E4)
.MODEL DX D(IS=1E-15)
.ENDS AD633
*$
*---------------------------------------------------------------LM7815C
.SUBCKT LM7815C Input Output Ground
x1 Input Output Ground x_LM78XX PARAMS:
+     Av_feedback=550, R1_Value=3060
.ENDS
*$
*
*** Voltage regulators (positive)
.SUBCKT x_LM78XX Input Output Ground PARAMS:
+       Av_feedback=1665, R1_Value=1020
*
* SERIES 3-TERMINAL POSITIVE REGULATOR
*
* Note: This regulator is based on the LM78XX series of
*       regulators (also the LM140 and LM340).  The model
*       will cause some current to flow to Node 0 which
*       is not part of the actual voltage regulator circuit.
*
* Band-gap voltage source:
*
*       The source is off when Vin<3V and fully on when Vin>3.7V.
*       Line regulation and ripple rejection) are set with 
*       Rreg= 0.5 * dVin/dVbg.  The temperature dependence of this
*       circuit is a quadratic fit to the following points:
*
*                                T         Vbg(T)/Vbg(nom)
*                               ---        ---------------
*                                0            .999
*                               37.5            1
*                               125           .990
*
*       The temperature coefficient of Rbg is set to 2 * the band gap
*       temperature coefficient.  Tnom is assumed to be 27 deg. C and
*       Vnom is 3.7V
*
Vbg 100 0 DC 7.4V
Sbg (100,101) (Input,Ground) Sbg1
Rbg 101 0 1 TC=1.612E-5,-2.255E-6
Ebg (102,0) (Input,Ground) 1
Rreg 102 101 7k
.MODEL Sbg1 VSWITCH (Ron=1 Roff=1MEG Von=3.7 Voff=3)
*
* Feedback stage
*
*       Diodes D1,D2 limit the excursion of the amplifier
*       outputs to being near the rails.  Rfb, Cfb Set the
*       corner frequency for roll-off of ripple rejection.
*
*       The opamp gain is given by:  Av = (Fores/Freg) * (Vout/Vbg)
*       where Fores = output impedance corner frequency
*                     with Cl=0 (typical value about 1MHz)
*             Freg  = corner frequency in ripple rejection
*                     (typical value about 600 Hz)
*             Vout  = regulator output voltage (5,12,15V)
*             Vbg   = bandgap voltage (3.7V)
*
*       Note: Av is constant for all output voltages, but the
*       feedback factor changes. If Av=2250, then the
*       Av*Feedback factor is as given below:
*
*                                 Vout     Av*Feedback factor
*                                 ----     ------------------
*                                   5          1665
*                                  12           694
*                                  15           550
*
Rfb 9 8 1MEG
Cfb 8 Ground 265PF
* Eopamp 105 0 VALUE={2250*v(101,0)+Av_feedback*v(Ground,8)}
Vgainf 200 0 {Av_feedback}
Rgainf 200 0 1
Eopamp 105 0 POLY(3) (101,0) (Ground,8) (200,0) 0 2250 0 0 0 0 0 0 1
Ro 105 106 1k
D1 106 108 Dlim
D2 107 106 Dlim
.MODEL Dlim D (Vj=0.7)
Vl1 102 108 DC 1
Vl2 107 0 DC 1
*
* Quiescent current modelling
*
*       Quiescent current is set by Gq, which draws a current
*       proportional to the voltage drop across the regulator and
*       R1 (temperature coefficient .1%/deg C).  R1 must change
*       with output voltage as follows:  R1 = R1(5v) * Vout/5v.
*
Gq (Input,Ground) (Input,9) 2.0E-5
R1 9 Ground {R1_Value} TC=0.001
*
* Output Stage
*
*       Rout is used to set both the low frequency output impedence
*       and the load regulation.
*
Q1 Input 5 6 Npn1
Q2 Input 6 7 Npn1 10
.MODEL Npn1 NPN (Bf=50 Is=1E-14)
* Efb Input 4 VALUE={v(Input,Ground)+v(0,106)}
Efb Input 4 POLY(2) (Input,Ground) (0,106) 0 1 1
Rb 4 5 1k TC=0.003
Re 6 7 2k
Rsc 7 9 0.275 TC=1.136E-3,-7.806E-6
Rout 9 Output 0.008
*
* Current Limit
*
Rbcl 7 55 290
Qcl 5 55 9 Npn1
Rcldz 56 55 10k
Dz1 56 Input Dz
.MODEL Dz D (Is=0.05p Rs=3 Bv=7.11 Ibv=0.05u)
.ENDS
*
*$