Problem

Troubleshooting guidelines for Transient convergence failure (time step too small error)

Solution

Common causes of convergence failure:

+ Lack of limiting

+ Rapid voltage transitions

+ Model discontinuities

+ ABM expression singularities

+ Large floating capacitors

To solve these convergence problems, try applying the following possible workarounds or solutions to your design.

1. Examine the simulator messages to look for clues as to why the problem occurs.

2. When specifying nonlinear device model parameters, be sure that a complete capacitance model is specified. Do not use ideal models which do not have capacitances.

3. Be sure to give source and drain areas for all MOSFETs, so that the junction capacitors and overlap capacitors are modeled.

4. Avoid large floating capacitors.

5. Use an ESR resistor with ideal inductors. Use the Step Ceiling to limit large time step predictions.

6. Increase the ITL4 option to 40 to increase the possible number of iterations at each time step.

7. Loosen the absolute tolerances for power circuits. This is most important for ABSTOL since its default is 1pA. As a rule of thumb, the absolute tolerances should not be more than 9 orders of magnitude smaller than typical signals present in the circuit. Failure to converge at the first time step is an indication of a dynamic range problem.

8. As a last resort, try different values for the Step Ceiling in hopes that the simulator will "jump" over a convergence problem.