OrCad Lite is stated as limited to 75 Nets; what defines a net - any circuit loop?
Strictly 75 nodes, one node being an isolated group of connected components, you get any connection to the "0" node for free. You can get a clue from the Output File, it lists the number of nodes in the circuit, and their names. There are some other restrictions as well, see the "demoswitch" documentation for more details. Exceeding the limits will reported in messages.
I am familiar with "Nodes", but the limitation refers to 75 NETS, not nodes. What is the definition of a NET?
Quote from OrCAD limitations document:
"You cannot save designs that have more than 75 Nets, including hierarchical blocks in the design."
Read on, you are looking at the Capture, not the PSpice limits. They effectively amount to the same thing once the netlist has been created.
Got it, thanks.
However, that still doesn't answer the question, what does a net consist of; a circuit loop?
Netlists are generally individual component lists (e.g. R1, N1, N2, 1K etc.) it's not a network. So it still not clear to me what is meant by a Net under Capture.
Did they really mean Node, instead of Net?
A Net is a connection betwwen two points. For example, if you connect R1 with R2, this connection will be a net. One Net has also a default Name or a particular one that you might have defined.
I hope it is clearer now.
Wouldn't connecting R1 to R2 be a NODE? Same as connecting R1, R2 & R3 would create a Node. I could see connecting two nodes together with a component; that would be an entry in the NETLIST (e.g R1, N1, N2, 1k). Then virtually each component would correspond to a net. According to the limitations OrCad Lite can simulate 75 nets, but only save 60 components. The limitations say you can simulate up to 75 nodes, but it hard to see how this is possible with a 75 Net limit which is sure to be reached before the 75 node limit.
I downloaded last version on 2019 and I can tell you about the limitation... It is complete s*&%^it, because they count ALL components (nodes) ever used in design. If you change something in the design it "cost" you node. I was testing some simple circuit- 8 transistors, 10 resistors, 2 caps, 2 sin sources and 2 VDC. After few component swap I received 75 nodes error. I reduced my schematics- still same error. I left ONLY one Vsin source and and R as load. Guess what? My design with two components still have more than 75 nodes.
Another problem- you have 4K monitor and lates "mandatory" windows 10 with 300$ video card? Forget- you can see how user interface draws those tiny buttons or just lost parts of the screen.
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