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#1 Apr 13, 2020
MQ_Xie
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Joined: 2020-04-13 22:41

Cadence CIS:WARNING(ORPSIM-15220): Error in opening Alias File

Dear Sir:

I faced an issue with Cadence CIS during simulation. 

It note as "WARNING(ORPSIM-15220): Error in opening Alias File" if I use hierarchical block. But everything is OK if I just copy the circuit in main circuit.

May you help to find the root cause?

(I know how to use hierarchical circuit, and other circuits I built with hierarchical blocks are OK. )

 

And some time, I will face "WARNING(ORNET-1123): Occurrence-specific properties". But the simulation can run well. I just courious what happened. 

So much thanks for your kind help in advance!

Thu, 2020-04-16 01:18
spice_up_your_c...
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Last seen: 3 years 9 months ago
Joined: 2020-01-26 09:49

Hi MQ,

Its hard to pin point as to why that might be happening just by the error message. If you could post the schematic, it may give a better idea in both cases

Wed, 2022-09-14 23:00
brianwilsonrt
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Joined: 2022-09-14 22:59

Hello, I read this nice article. I think You put a best effort to write this perfect article. I appreciate wordle 2 your work. thank you so much. 

Wed, 2023-08-09 03:58
andree23
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Joined: 2023-04-17 05:46

Verify that the alias file referenced by the swiftle hierarchical block is accessible and correctly linked. Ensure that the alias file's path and name are accurately specified in your hierarchical block setup.

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