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#1 Mar 2, 2021
sourav
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Last seen: 4 months 3 weeks ago
Joined: 2017-07-29 06:48

How to change initial state of a digital node from 0 to 1

Hello Everyone,

I want to simulate the following circuit:

Here, Propagation delay of D Flip flops are 0 and propagation delay of XOR Gate is 3 ns

Furthermore clock frequency is 500 MHz and the initial states are D2=1 ,Q2=Q1=Q0=1

My Source Code for the same is:


.lib "C:\Cadence\SPB_16.6\tools\pspice\library\dig_io.lib" 
U_CLK STIM( 1, 1 ) $G_DPWR $G_DGND ;to generate a Clock Pulse
+ CLK 
+ IO_STM
+ 0s 0
+ REPEAT FOREVER
+ +1ns 1 
+ +1ns 0 
+ ENDREPEAT
*
U2 DFF(3) $G_DPWR $G_DGND $D_HI $D_HI CLK
* Three Synchronous D flip-flops
+ D2 Q2 Q1 Q2 Q1 Q0 QBAR2 QBAR1 QBAR0
+ T_DFF IO_STD
.MODEL T_DFF UEFF
*
U_G1 XOR $G_DPWR $G_DGND Q0 Q2 D2
+ T_XOR IO_STD
.MODEL T_XOR UGATE 
+ TPLHMN=3ns TPLHTY=3ns TPLHMX=3ns
+ TPHLMN=3ns TPHLTY=3ns TPHLMX=3ns
+)
*
.TRAN 1ns 30ns 
.PROBE D(CLK) D(Q2) D(Q1) D(Q0) D(D2)
.OPTIONS DIGINITSTATE=1
.END

 

Simulation Result:

Now, the above code is assigning the initial state of D2=0;

I have tried .NODESET and .IC commands but none of them work with digital nodes,

so how can i assign initial state of D2=1 ?

Mon, 2021-05-17 04:47
alok
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Last seen: 2 weeks 1 day ago
Joined: 2016-05-10 23:49

You can try setting DIGINISTATE to 1. You can set this under simulation setting > Option> Gate Level Simulation 

Initialization - By default, at the beginning of each simulation, all flip-flops and latches are initialized to the unknown state (that is, they output an X). Each device remains in the unknown state until explicitly set or cleared by an active-low pulse on either the preset or clear pins, or until a known state is clocked in. You can override the X start-up state by setting .OPTIONS (analysis options) on page 71 DIGINITSTATE to either zero or one. If set to zero, all flip-flops and latches in the circuit are cleared. Likewise, if set to one, all such devices are preset. Any other values produce the default (X) start-up state. The DIGINITSTATE option is useful in situations where the initial state of the flip-flop is unimportant to the function of the circuit, such as a toggle flip-flop in a frequency divider.

 

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