i have made one resonant circuit which is in input of three phase inverter ,it will be used to do zero voltage switching for all switches of three phase inverter.
actually i want to start that resonant circuit between two active switching states of the inverter. but pulse width will be differerent for all switches in all six sectors . so can i interface this circuits using verilog hdl code . i am asking this , because i have not learnt verilog hdl till now.