Hello! I am currently working on a design for a buck converter for a project. I am utilizing a LM3150 buck IC to step a Vin with a nominal voltage of 24V to 5V @ 12A.
I have used the TI Power Designer to generate a schematic based upon my requirements, shown below:
The resulting steady state waveform for the output voltage plotted in the Webench tool is shown below:
I decided to simulate the schematic in Pspice for TI. The schematic used and resulting output voltage is shown below:
Between the two simulations, there seems to be about a 2.5V difference in the resulting output voltage between the Pspice for TI and Webench simulations. Could the issue be the type of solver that the solvers use for their analysis or is it something im overlooking?
Thanks!
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It comes same for me in PSpice for TI as well.
Open reference design in PSpice for TI and run its steady state simulation and check.
For that you can directly search for part LM3150 in pspice part search in PSpice-for-TI and right click on LM3150 -> select "open model test circuit" and open LM3150_TRAN transient model, it will download and open the LM3150 reference design, change the feedback resistor divider circuit values and others as needed as per the calculation to achieve your desired output and simulate it.
The simulation in PSpice-for-TI also gives correct results
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