Current sensors are utilized to sense current both AC and DC and generate an output signal which is proportional to the current sensed.
This application note is developed, based on the datasheet for IC part Si85xx manufactured by Silicon Labs.
Overview
This application note has:
Device Overview
This device series has unidirectional current sensing devices that are available in the range of 5 to 20 A current. In this document, we will cover the simulation models for SI850X and SI851X series. The device comes in two model packages si850x and si851x series. The difference between the two device package is the SI851x series has the FAULT pin which provides additional functionality. The X here denotes the device part number which is according to the current sensitivity. The sensitivity relation to the part name is given in the following table.
In the case of the IC model, parameter sensitivity is provided. By varying the value of this parameter you can select the IC model. Both the series are covered in this document.
Where to Find This Model
The symbols for these two parts are available in the SPECIAL_PURPOSE_ICS library at the following location:
<INSTALLATION>\TOOLS\CAPTURE\LIBRARY\PSPICE\SPECIAL_PURPOSE_ICs.OLB
OrCAD Capture and PSpice Design Example
Startup operation
Figure 1 shows the typical application circuit diagram for the SI850x series. It is a synchronous buck topology that is down-converting 100 V to 50 V. Select the Si8501_single_ended_mode-Tran simulation profile and simulate the testbench. Place the probes as seen in Figure 2.
Figure 1: Single-ended mode opration for the Si850X series
Figure 2: Simulation output for buck converter
Device Startup Operation
Figure 3 shows the startup operation of Si850x/Si851x.
Figure 3: Si850x/Si851x Startup operation
Where:
Here it would be 150 ns due to the 15 k resistor connected to the TRST pin. From Figure 3, you can see that the output is measured only during the measurement duration highlighted in green.
Simulate the testbench in Figure 2 with the Si8501_single_ended_mode-Tran simulation profile. Place the probes and adjust the time scale according to the next figure (Figure 4a).
Figure 4a: Adjusted time scales in the probe window
Figure 4b: Adjusted time scales in the probe window
The duration from where the power good is initiated on VDD to where the output is sensed and can be clearly seen to be 150us + 150ns approximately (highlighted in Figure 4b).
As this a current sensor, the current is sensed and given to the output pin as scaled voltage, scaled by factor as defined by the sensitivity factor value, here it is ‘0.404’.
Figure 5: Sensed current in-terms of voltage
As seen in Figure 5, the output voltage seen by probe V(U1:OUT) is a scaled voltage value of current I(U1:IIN) as per the sensitivity.
i.e. V(U1:OUT) = I(U1:IIN)* ‘sensitivity’
Figure 6: Simulation output for input and Output
Leading Edge Noise Suppression
As seen in Figure 6, the leading edge noise suppression technique eliminates the leading edge spikes observed in the sensed output voltage. Also, observe that there is a finite amount of delay between the input pulse and the observed output voltage pulse. Here it is approximately 90 ns.
Output Modes
Current sensors generally have more than one output pins from where the sensed output voltage is obtained. This output can then be interfaced with subsequent devices to complete the systems. The IC model has various output modes that govern the routing of the sensed current to different output pins. The supported modes are:
• Si850x
o Single Output Mode
• Si851x
o Single output mode
o 2 wire ping pong
o 4 wire ping pong
In this document, setup for a 4-wire ping-pong mode specific to Si851x device series is demonstrated. In the ping-pong mode, the current is sensed and is routed to output pins based on the reset input pins R1, R2, R3, and R4, as seen in the table in Figure 6.
Here, current would appear on the OUT1 pin when R1 is High and R2 is low, and on OUT2 when R3 is High and R4 is Low. As you can see, Reset means that there would be no measurement output from the output pins.
Figure 6: Output mode table
Figure 7 shows the application circuit schematic for the 4-wire ping-pong mode.
Select the fullbridge_mode-Tran simulation profile. Simulate the testbench and observe the results.
Figure 7: Testbench for the 4-wire ping-pong mode
Figure 8: Simulation results for the 4-wire ping-pong mode
From the simulation results, you can see that the current measurement follows the patterns as described in the output mode table (Figure 7). There is no output when is a Reset condition. I (U1: IIN) is the current to be measured and V (U1:OUT1) V (U1:OUT2) probes correspond to sensed output voltage.
Watchdog Timer and Fault Output Option
This model has the capability to assert the FAULT condition when the RESET duration exceeds a time limit. This condition usually signifies system faults. The Fault is asserted and the voltage on FAULT pin is pulled low. (This ‘FAULT’ pin is available only in SI8501X IC model)
Figure 9 shows the setup for FAULT condition assertion.
Figure 9: Simulation for FAULT condition assertion
Select the single_ended_mode-Tran simulation profile. Simulate the testbench and observe the results.
Place the probe or plot the traces as shown in the following figure.
As per the test setup, this model IC is working in single-ended mode (Figure 6). Within the duration 6 ms to 7 ms, all inputs R1, R2, R3, and R4 are zero asserting a long reset duration. The Reset is asserted from 6 ms, and at 6.044 ms the fault pin is pulled down. As the reset condition extends beyond the watchdog timer duration, which is 44u s, the fault is pulled low.
fault condition is cleared at 7ms once the voltage on pin R1 returns to its original voltage level, and the device is out of RESET phase and into measurement state.
Limitations of the Model Implemented in PSpice
The following known limitations exist at this time:
References
This document is based on the SI850X and SI851X series datasheet.
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