Simulating TLE8110EE the Smart Multichannel Low-Side Switch with Parallel Control and the SPI Interface

Smart power switches are mostly used in the automotive and Industrial applications. An ideal power switch requires low resistance and high voltage tolerance to operate any system properly.  Smart switches enhance the capability of non-ideal switches by incorporating rich features, such as fuse function, loading diagnostics, load controlling, multiple switches in single package, inbuilt parallel and serial interface (SPI), and so on.


This application note has:

  • A brief overview about the TLE8110EE device and its model
  • A design example for OrCAD Capture and PSpice that demonstrates the following:

    • 16 bits SPI communication
    • 16 bit supported commands

      • CMD commands
      • DCC commands
      • OUTx register control commands
      • PMx commands
  • Reset and enable functioning of the IC model

About the Device

TLE8110EE is an automotive IC that is used in power-switch automotive and industrial systems, switching solenoids, relays, and resistive loads. It has 10 channel low-side switches with serial peripheral interface (SPI) and 10 open-drain MOS output stages. The output stages are controlled using parallel input pins for pulse width modulation (PWM) use, or Serial Peripheral interface (SPI) Interface. TLE8110EE is protected by embedded protection functions and is particularly suitable for engine management and powertrain systems with setup as shown in Figure1.


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Figure 1: Setup of the IC in design environment interfaced with microcontroller and switch control relays.

Referring to Figure 1, here is how the switches operate various loads in the automotive environment:

  • Cooling fan relay
  • Fuel pump relay
  • Start relay
  • Climate control relay
  • Fuel injectors for engine

Using this model offers the following key features:

  • 16-bit SPI

    • ​Diagnosis for SCG (short to ground), OL (open load) and SCB (short to battery)
    • ​Over-Current Protection (switch-off)

OrCAD Capture and PSpice Design ­­Example

Startup operation

Figure 2 shows the schematic for the model using which we will simulate and analyze how this IC model functions. A few pointers about this schematic:

  • The command given to the model is by digital stimulus that has been connected to the SPI control pins and emulate the microcontroller operation.
  • All loads are resistive.

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Figure 2: Schematic for the TLE8110EE Model

Device Operation

16 bit SPI Interface

The diagnosis, control, and monitoring of the IC is based on serial peripheral interface (SPI). The SPI block works on serial mode full-duplex synchronous communication, the pins used in SPI are S_SO, S_SI, S_CLK, and S_CS. Data is sent and received by the S_SI and S_SO data lines from the model at the data rate given by S_CLK. When the falling edge of S_CS is encountered, the S_SI pin begins to access the data at every falling edge of the S_CLK, and at the same time the data is transferred out on pin S_SO at the rising edge of the S_CLK.


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Figure 3: Waveforms on pins used in the SPI Block

Select the SCHEMATIC-SPI_test profile and run the simulation. You get simulation results as shown in Figure 4.

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Figure 4: Simulations results

The wave form at the S_CS pin goes low at 19.736 us and the IC starts to accept the data input at the S_SI pin. Simultaneously, the output can also be observed at the S_SO output pin of the model. In this way, we see serial communication in full-duplex mode. This serial communication takes place for the duration between 19.736 us to 22.937 us, as seen in Figure 4, until the S_CS pin is in the low state.

16-bit Data Frame

The data accepted on the S_SI pin by the IC model is a 16-bit data frame. The data frame sent back is dependent on the previous command which was received by the S_SI pin. Figure 5 shows the data I/O between master and the model IC.

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Figure 5: Data transfer between the master and the model IC

Figure 6 shows the typical simulation result of data frames sent and received.

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Figure 6: Simulation result

Figure 7 shows the 16-bit input data frame stucture.

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Figure 7: Input data frame structure

Serial output command frame structure (S_SO)
16-bit output command Frame

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Figure 8: Output command frame

Overview  of Register and Command

The unique commands given to this IC via SPI communication carry out their various actions. The internal register stores the information provided by these commands, and also stores the  information regarding the various status and fault condition in the IC.  When this IC is started, the internal registers are loaded with default values. The value of these registers is updated each time a defined command is received by the S_SI pin or when there is a fault condition detected by the IC.

Figure 9 lists all the command supported by this model IC and their bit structure.

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Figure 9: Supported commands with their bit structure

CMD Commands

CMD commands are send to the device using the address range bits [14:12] =’000’. After validating the commands, the device sends the feedback in the next SPI SO frame. The lists of commands under CMD are listed in Figure 10.

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Figure 10: List of CMD commands

CMD_RINX- command: Return Input Pin (INx) -Status

This command enables the external microcontroller device to read out the status of the input pins in TLE8110EE.  Figure 11 shows the serial output frame, given as feedback to CMD_RINX.

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Figure 11: Serial output frame as feedback to CMD RINX

The command is sent via S_SI pin within the time duration 56.055 n to 3.9732 u. The response to this is sent in next S_CS low cycle within time duration 4.5636 u to 7.7636 u.

Select the SCHEMATIC1-CMD_RINX simulation profile and run the simulation.

As seen from the simulation results (Figures 12 and 13), all the bits from 0 to 9 in the output frame are high, which denotes that all the inputs are in a healthy state.

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Figure 12: Simulation results - part 1

Now in the schematic, modify the V140 pulse source. Change the V2 = 1, and rerun the simulation. You can now see that the 6th bit, which corresponds to IN7 input, becomes ‘0’ indicating a low-voltage state on the IN7 port.

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Figure 13: Simulation results - part 2

CMD_RSD Command: Return Short Diagnosis

When this command is sent, the IC returns the OR-operated short-Diagnosis of each channel (OUT1-OUT10), in the next SPI frame. The short-diagnosis register is set whenever there is an SCG (short to ground), OL (open load), and SCB (short to battery) from the output side. Figure 14 shows the serial output frame that is given as feedback to CMD_RSD.

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Figure 14: Serial output frame given as feedback to CMD RSD

Now, change to active profile to SCHEMATIC1-CMD_RSD and simulate the design. Figure 15 shows the simulation result. This command is sent between the duration 12.134 us to 15.344 u. The response for this is received between the time duration 15.931 us to 19.162 us.

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Figure 15: Simulation result

Now, in the schematic, edit V2=5 in voltage vpulse source V135, and, simulate the testbench. The vpulse along with the switch setup creates a short condition at 6 us and this status gets stored in the models internal short diagnosis register. In Figure 16, observe that the first bit SD2 is high, denoting a short condition on channel 2.

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Figure 16: Simulation result with modified V2

DCC -Diagnosis and Compact Control Commands

This command set enables reading out and clearing the diagnosis register whenever there is fault condition in the output channel. The commands supported by the TLE8110EE model are listed in Figure 17

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Figure 17: DCC commands supported

Diagnosis Register

The TLE8110EE model has two diagnosis register banks, namely, DRA and DRB.  DRA is for channel 1 to 6 and DRB is for channel 7 to 10. On RESET the value of these register is set to 000­h.  

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Figure 18: Diagnosis register DRA and DRB


Each time this command is sent, the content of the DRA register is sent back as a response in the next SPI frame.

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Figure 19: Serial output frame feedback to DCC DRA

Select the SCHEMATIC1-DCC_DRA as the simulation profile and run the simulation. This time, observe that there is short condition at 6 us on channel output 2. The DCC DRA command is sent within the time duration 4.5636 us to 7.7636 us. The output for this is acknowledged between 8.3334 us to 11.563 u. Note the output bits 10.800u onwards, here 01 denotes an open load condition on channel output 2.

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Figure 20: Simulation results

The DCC_DRB command is similar to DCC_DRA but for channel 7-10.

ISx - Input or Serial Mode Control Registers (ISA and ISB)

The INPUT or Serial Control Register [ ISx[1:0] ], enables you to control the output channels. There are four setting options possible:

  • Standard Serial Control: the related output channel is set according the content of the OUTx register.
  • Direct control by the input pins.
  • The settings of the parallel mode register PMx[0].
  • AND operation between the OUTx register and signals at the INPUT Pin.

There are two registers ISAx and ISBx. SAx allows control over channel 1 to 6, and ISBX allows control over channel 7 to 10.

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Figure 21: ISAx and ISBx register content

Select the SCHEMATIC1-ISAX sim profile and run the simulation. You should get the following simulation output.


The ISAx command is sent in between 42.5 us to 44.9 us. For channel 5, initially, the output pin was controlled by input pin. On sending the ISAx command, we changed the value of IS5 to ‘01’. As the default value of the controlling register for Output channel is ‘0’, the channel 5 is turned off at S_CS low to high transition at 45.9 us, when the ISAx command is decoded. A similar scenario is observed on Out3.

OUTx - Output Control Register

The output control register, controls all the 10 output channels. Each bit switches ON or OFF the related channel. OUTx register becomes active only when set by ISx[1:0] =0x, as explained earlier. 

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Figure 22: Control model change by ISAx commands

Initially, channel OUT5 is OFF. The command frame for OUTx is sent at 46 us to 49.5us on S_SI. In this frame, the value of OUT5 is 1 and OUT3 is 0, therefore, at S_CS low to high at 49.5 us, channel 5 is turned ON, whereas OUT3 remains OFF.

PMx - Parallel Mode Register CHx

Parallel mode register PMx[1] informs TLE8110EE about the externally connected output channels.

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Figure 23: PMx register structure

Select the SCHEMATIC1-PMX simulation profile and run the simulation.


The PMX command is received within the time frame 49.5 us to 53 us. Initially, channel 4 is ON. In the command, the value of PM34=1 which makes channel 3 and 4 parallel, and both these channels are controlled by the input of channel 3. When S_CS goes low to high at 53us, the channel 4 is turned OFF, because the input pin of channel 3 has a low signal.

Reset and Enable Inputs

TLE81100EE is equipped with RESET [RST] and ENABLE [EN] pins. Both these pins work with VCC (digital supply) and VDD (analog supply) to trigger an internal reset or disable the control of the TLE8110EE model.

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Figure 24: Block diagram for RST and EN pins operated with VCC and VDD

In this schematic:

  • Reset pin [RST]
    Acts as the main reset for the Model. It is triggered when the RST pin is pulled low, or if there is an under-voltage condition at VCC. It resets the whole device including the control register.
  • Enable pin [EN]
    Resets only the output channel. It is triggered when the RST pin is pulled low, or if there is an under-voltage condition at VDD. The Information in the registers and all SPI communication remains intact.

Figure 25 shows the response of channel OUTx when the EN pin pulled low (note time scale axis value needs to be changes accordingly to view the waveforms).

Select the SCHEMATIC1-Reset_and_Enable simulaiton profile and run the simulation.

Now, you will observe that the VDD pin goes low at 1.2021 m, which asserts a system-wide reset. Once VDD reaches the power good level, the model does not power up until the internal reset is cleared. This is acchieved by sending the CSDS_CMD command over S_SI. Observe this between 449.727 us  and 450.600 us. The reset is cleared, and the reset voltage jumps at 459 us to indicate the power good state.

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In the same simulation, observe the simulation results from 1 ms to 2.2 ms. You see a response of channel 10 for low signal at the EN pin at 2.0 ms. It is observed that the response of Channel 10 to RST and EN pins has delays. These delays are tRST (Minimum reset duration time RST) and tEN (Minimum enable duration time EN). In the case of EN, when EN becomes high, channel 6 turns ON again after tVDDO (Analogue Supply Power-on Delay Time).

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Figure 25: Response of channel OUTx when the EN pin pulled low

Overload Shutdown Thresholds and Delay Times

If an overcurrent or overload is detected on a channel, the channel is turned OFF. The channels are turned OFF after a certain overload shutdown delay time duration, which varies depending upon the threshold range of the over current.

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Figure 26: Overload shutdown thresholds and delays

Select the SCHEMATIC1-over_load_cond simulation profile and run the simulation.

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Figure 26: Overload shutdown thresholds and delays

The current in channel 3 increases beyond the high-level current threshold, but decreases below the threshold within 14 us. Since 14 us is less than the short overload shutdown delay time (tOFFcl_h=21 us), the channel shuts down after the long overload shutdown delay time (tOFFcl_h=40us).

Note that additional simulation profile have beed provided in the testbench which correspnd to the rest of the command mentioned in the datasheet

Limitations of Model Implemented in PSpice

The following known limitations exist at this time:

  • 8-bit SPI communications and commands are not supported in this model
  • The 'DEVS' command and its register are not supported in this model
  • Some of the electrical characteristics and values in the datasheet might not match the model
  • Temperature effects are not modeled


  1. TLE8110EE Datsheet





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